IEC 60749-29:2011
Semiconductor devices - Mechanical and climatic test methods - Part 29: Latch-up test
Semiconductor devices - Mechanical and climatic test methods - Part 29: Latch-up test
- Статус документа:
- Действующий
- Формат:
- Электронный (PDF)
- Количество страниц:
- 48
- Дата публикации:
- 7 апреля 2011 г.
- Издание:
- IEC IS 60749 edition 2 version 1
- ICS:
- 31.080.01
IEC 60749-29:2011 covers the I-test and the overvoltage latch-up testing of integrated circuits. The purpose of this test is toestablish a method for determining integrated circuit (IC) latch-up characteristics and to define latch-up failure criteria. Latch-up characteristics are used in determining product reliability and minimizing "no trouble found" (NTF) and "electrical overstress" (EOS) failures due to latch-up. This second edition cancels and replaces the first edition published in 2003 and constitutes a technical revision. The significant changes with respect to the previous edition include: - a number of minor technical changes; - the addition of two new annexes covering the testing of special pins and temperature calculations.
Abstract
Overview
IEC 60749-29:2011 is an international standard published by the International Electrotechnical Commission (IEC) that defines mechanical and climatic test methods specifically focused on the latch-up testing of semiconductor devices, particularly integrated circuits (ICs). This standard provides a comprehensive procedure for performing I-test and overvoltage latch-up testing on CMOS devices to determine their latch-up characteristics and define failure criteria.
The primary objective of IEC 60749-29:2011 is to establish reliable, repeatable test methods that help manufacturers assess and minimize latch-up-related failures. These failures often manifest as "no trouble found" (NTF) or "electrical overstress" (EOS) issues in semiconductor products, impacting device reliability and increasing warranty costs.
This second edition updates the original 2003 release with minor technical revisions and additional annexes focused on testing special pins and temperature calculations.
Key Topics
-
Latch-Up Definition
Latch-up refers to a parasitic thyristor effect in ICs that creates a low-impedance path, causing abnormal current flow and potential device malfunction. Once triggered by an overstress condition such as a voltage or current spike, this state persists even after removing the trigger. -
Test Types
- I-test: Applies positive and negative current pulses to pins under test to provoke latch-up conditions.
- Overvoltage Test: Applies supply voltage levels above the maximum rated voltage to detect latch-up failures.
-
Failure Criteria
The standard defines clear criteria for latch-up failure to help distinguish between safe operating boundaries and destructive conditions. -
Test Procedure
Detailed workflows cover setup, device under test (DUT) preparation, current and voltage application, and monitoring of leakage and supply currents. The procedure involves preconditioning pins and recording current surges or device malfunction. -
Classification & Levels
Latch-up susceptibility is classified according to temperature and operating conditions, and test levels define the severity and type of latch-up triggering stimulus applied. -
Special Pins & Temperature Calculations
Annexes outline the handling of special pin types connected to passive components and provide methods for calculating operating ambient or case temperatures consistent with junction temperature limits.
Applications
IEC 60749-29 is crucial for semiconductor manufacturers, quality assurance engineers, and reliability testing laboratories aiming to:
- Enhance product reliability by identifying and mitigating latch-up vulnerabilities in CMOS ICs.
- Reduce returns and field failures by minimizing latch-up induced NTF (no trouble found) or EOS (electrical overstress) events.
- Meet industry compliance with recognized international standards for latch-up testing in semiconductor devices.
- Optimize IC design through characterization of latch-up characteristics, aiding in design decisions and protective circuitry implementations.
- Benchmark device robustness across temperature variations and overvoltage conditions relevant to real-world applications.
Industries such as consumer electronics, automotive, aerospace, and industrial control systems benefit significantly from adherence to this standard to ensure durable and stable semiconductor performance.
Related Standards
IEC 60749-29:2011 is part of the larger IEC 60749 series which addresses various mechanical and climatic test methods for semiconductor devices. Related standards within this series may cover:
- Mechanical stress testing – shock, vibration, and mechanical endurance tests.
- Climatic conditions testing – temperature cycling, humidity, and moisture resistance.
- Electrical overstress tests – electrostatic discharge (ESD), electrical fast transient (EFT), and other electrical robustness evaluations.
Other standards that complement IEC 60749-29 in semiconductor device qualification and reliability include:
- JEDEC JESD78 – standard for latch-up testing in ICs.
- ISO 26262 – functional safety for automotive applications, often requiring latch-up testing compliance.
- IEC 60068 series – environmental testing for electronic components.
Adherence to IEC 60749-29 in conjunction with these complementary standards provides a comprehensive reliability framework for modern semiconductor devices.
Keywords: IEC 60749-29, latch-up test, semiconductor device testing, integrated circuits, CMOS reliability, latch-up failure criteria, I-test, overvoltage test, electrical overstress, NTF reduction, semiconductor standards, mechanical and climatic test methods.
Технические детали
- Технический комитет
- TC 47 - Semiconductor devices
- SKU
- IEC 60749-29:2011
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