IEC 61188-5-4:2007

Overview

IEC 61188-5-4:2007 is an IEC standard that defines component and land‑pattern dimensions for small outline integrated circuits with two‑sided J leads (SOJ) intended for the reflow soldering process. The standard covers basic SOJ construction, lead terminology (heel, toe), component dimensional ranges (examples: SOJ/300, SOJ/350, SOJ/400, SOJ/450) and the tolerances and target solder joint fillet dimensions used to derive recommended PCB land patterns.

Key topics

• SOJ component description: body sizes (inches/mm), lead counts (14–28 pins), and uniform pitch (1.27 mm). Leads must be coplanar within 0.1 mm.
• Land pattern dimensioning: recommended land geometries for reflow-assembled SOJ packages. Land patterns are derived from a mathematical tolerance model and specified land protrusions and courtyard excesses.
• Threefold land options: Level 1–3 sizing (maximum, medium, minimum) based on different land protrusion and courtyard excess choices to suit process variations.
• Solder fillet design: toe, heel and side fillet shapes and minimum/median/maximum dimensions are specified to balance reliability, quality and manufacturability.
• Process considerations: guidance for solder alloy considerations (lead‑free vs. tin‑lead) and reflow profiles; notes on wave soldering (uncommon for SOJ) - if used, land/courtyard adjustments and solder thieves may be required.
• Packaging and handling: reference to tape, stick and tray packaging for automated assembly (bulk packaging not recommended).

Practical applications

• Designing PCB footprints and land patterns for SOJ (J‑lead) components in SMT assemblies.
• Establishing manufacturable footprints for memory ICs and other dual‑row devices that use J leads.
• Verifying solder joint fillet geometry for process qualification, assembly yield optimization and reliability testing.
• Adapting footprints when migrating to lead‑free alloys or when aligning with specific assembly process conditions.

Who should use this standard

• PCB layout engineers and CAD library creators
• Process and manufacturing engineers in SMT assembly lines
• Component engineers and reliability/test teams
• Contract manufacturers (CMs) and OEMs producing boards with SOJ packages

Related standards

• IEC 61188‑5‑1 (generic land/joint requirements methodology)
• IEC 60068‑2‑58 (solderability and soldering heat tests)
• IEC 61760‑1 (SMD specification method)
• IEC 60286 series (component packaging for automatic handling)

Keywords: IEC 61188-5-4, SOJ, J leads, land pattern, reflow soldering, solder joint fillet, PCB footprint, surface mount, SMT, printed boards.