IEC 61523-1:2023

Overview

IEC 61523-1:2023 - Delay and power calculation standards, Part 1: Integrated Circuit (IC) Open Library Architecture (OLA) - is an IEC/IEEE dual‑logo standard (published as IEEE Std 1481) that defines a common architecture and data interfaces for delay and power calculation in integrated circuit design. The standard supports modeling of logical behavior and signal integrity, and specifies language, procedural interfaces, and parasitic data formats to improve interoperability between EDA tools and compiled library descriptions.

Key topics and requirements

• Delay Calculation Language (DCL): A descriptive language for timing and power modeling. DCL defines syntax, data types, mathematical statements, and timing propagation mechanisms used to express delay, slew, and power characterization.
• Procedural Interface (PI): A standardized software API for communications between EDA applications and compiled libraries of DCL descriptions, enabling tool-to-library interoperability and consistent invocation of timing/power models.
• Standard Parasitic Exchange Format (SPEF): A file exchange format for parasitic information about chip designs (resistances, capacitances, net topology) used in delay and signal‑integrity calculations.
• Informative examples and notes: Usage examples, context and conventions, and guidance to help implementers adopt DCL, PI and SPEF consistently.
• Scope and structure: Includes lexical rules, predefined types/variables, built-in functions, timing checks, and library/application parallelism considerations.

Keywords: IEC 61523-1, IC Open Library Architecture, delay calculation language, DCL, SPEF, procedural interface, delay and power calculation, signal integrity.

Practical applications

• Standardizing timing and power characterization of standard cell and IP libraries for use across multiple EDA tools.
• Enabling accurate delay, slew and power estimation during static timing analysis, signoff flows, and early architecture studies.
• Facilitating exchange of parasitic and library data between extraction tools, timing engines, and signal‑integrity analyzers using SPEF.
• Supporting automation in library development (PDK/IP vendors) and compiled model deployment in ASIC/SoC flows.

Who should use this standard

• EDA tool developers implementing timing/power engines or library interfaces.
• Library/IP vendors and PDK authors creating DCL-based models and compiled libraries.
• Timing, power and signal-integrity engineers working on characterization, signoff, and interoperability across toolchains.
• Systems architects and verification teams requiring consistent delay and power data exchange.

Related standards

• IEEE Std 1481 (integrated as dual‑logo)
• Other parts of the IEC 61523 series addressing complementary aspects of delay and power calculation and tool flows.

IEC 61523-1:2023 provides a practical foundation for consistent, interoperable delay and power modeling in modern IC design flows, improving accuracy and portability across EDA toolchains.