IEC 61523-4:2015

Overview

IEC 61523-4:2015 - Design and Verification of Low-Power Integrated Circuits defines a standard format for expressing the low‑power design intent of electronic systems and IP. Published in alignment with IEEE Std 1801™-2013, this document formalizes the Unified Power Format (UPF) style approach to specify power architectures, supply networks, power switches, isolation, retention, and power states - and the relationship between power intent and logic captured in HDLs. IEC 61523-4 enables consistent, tool‑friendly power intent description for design, verification, and simulation of low‑power integrated circuits.

Key topics and technical requirements

• Power intent specification: A standardized format to describe supply nets, supply sets, power domains, and how they interconnect.
• Power management elements: Definitions and mapping for switches, isolation cells, level shifters, retention cells, always‑on domains, and other power management cells.
• Power states and simstates: Formal representation of operational states (on/off/retention/etc.) and simulation semantics for state transitions.
• Design representation & refinement: Mechanisms to relate UPF power intent to HDL logic (successive refinement, file structure, and name/element scoping).
• Verification and simulation semantics: Rules for creation and simulation of the supply network, power state behavior, and error checking in EDA flows.
• Language and command model: UPF as a command-based language (Tcl‑based) with defined lexical elements, attributes, and processing phases for tools.
• Processing & tool flow: Data requirements, processing phases, and expected tool behavior for importing, refining, and applying power intent during synthesis, simulation, and verification.

Practical applications and users

IEC 61523-4 is used by:

• IC architects and system designers to capture power intent across chips and subsystems.
• RTL designers and IP integrators to map power domains and ensure correct logic-to-power relationships.
• Verification engineers to drive power-aware simulation, power intent validation, and sign-off checks.
• EDA tool vendors to implement UPF support for synthesis, simulation, formal verification, and power network analysis.
• SoC integrators for consistent handoff of power intent between teams and tools, improving interoperability and reducing integration risk.

Practical value includes enabling power‑aware verification, automating power net generation, ensuring correct isolation/retention behavior, and supporting low‑power sign‑off workflows.

Related standards

• IEEE Std 1801™-2013: The IEEE standard aligned with IEC 61523-4 and often referenced for UPF implementations and tooling.

Keywords: IEC 61523-4, UPF, Unified Power Format, low-power design, power intent, power states, power management, power verification, IEEE 1801, integrated circuits.