Overview
IEC 62530-2:2021 - SystemVerilog Part 2: Universal Verification Methodology Language Reference Manual specifies the Universal Verification Methodology (UVM) as a formal language reference. It establishes the UVM application programming interfaces (APIs) and a Base Class Library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The standard is a double‑logo IEC/IEEE publication and is based on the IEEE SystemVerilog language (IEEE Std 1800™).
Key Topics
This language reference documents the UVM API and class library in detail and organizes content into clear technical areas, including:
- Base classes and fundamental types (e.g., uvm_object, uvm_transaction, uvm_time)
- Reporting and recording mechanisms (uvm_report_message, report server, uvm_tr_database)
- Factory and object/component wrappers to support flexible construction and substitution
- Phasing and synchronization (predefined phases, domain management, objections)
- TLM interfaces for component communication (UVM TLM 1 & 2)
- Sequencing and sequencer classes (uvm_sequence, uvm_sequencer, sequence library)
- Predefined component classes (uvm_component, uvm_agent, uvm_driver, uvm_monitor)
- Policy utilities (printers, comparers, packers, copiers)
- Register layer and register model (uvm_reg_block, uvm_reg_map, uvm_reg_field, uvm_mem)
- Callbacks, barriers, pools and container classes to support modular verification architectures
These topics reflect the document’s table of contents and show the scope of the standardized APIs and class behaviors used in UVM-based verification.
Applications
IEC 62530-2:2021 is aimed at organizations and professionals who build or use SystemVerilog verification environments:
- Verification engineers developing functional verification testbenches for ASICs, SoCs, and FPGAs
- EDA tool vendors implementing or supporting UVM-compatible simulators, utilities, and libraries
- Hardware design teams who need standardized testbench components for reuse and interoperability
- Quality and validation teams establishing verification flows and regression frameworks
Using this standard helps teams create modular, scalable, and reusable verification components, accelerate testbench development, and improve cross‑tool compatibility.
Related Standards
- IEEE Std 1800™ (SystemVerilog) - the foundational language on which the UVM APIs are based
- IEC/IEEE double‑logo relationship - IEC 62530-2:2021 is published in conjunction with the IEEE UVM language standard
Keywords: IEC 62530-2:2021, UVM Language Reference Manual, Universal Verification Methodology, SystemVerilog, UVM, verification environment, TLM, register model, Base Class Library (BCL), APIs.