IEC TR 63133:2017

Overview - IEC TR 63133:2017 (Scan based ageing level estimation)

IEC TR 63133:2017 provides a technical-report level design technique for scan based ageing level estimation in semiconductor devices. It specifies the architecture and operation of a performance estimation storage element (PESE) that monitors semiconductor ageing (modelled as path delay) and characterizes an ageing level. The estimated ageing information is intended to improve system reliability in safety- and mission‑critical applications.

Key keywords: IEC TR 63133:2017, scan based ageing level estimation, semiconductor ageing, performance estimation storage element, ageing level monitoring.

Key topics and technical requirements

• Ageing model and terminology: Defines terms such as transistor ageing, ageing level, guard band, scan cell, and related abbreviations (PE, PECLK, PERC, PESE).
• Ageing-level estimation principle: Ageing is modelled as increased signal/path delay. Multiple delay points are monitored to locate the boundary between pass and fail states within a defined guard band.
• Scan‑based monitoring architecture: Uses scan cells, scan chains, and DFT mechanisms to integrate ageing detectors into existing test access flows.
• Phase‑shifted clock and shadow latch: Introduces a shadow latch sampled by a phase‑shifted clock (PECLK) to detect incremental delay relative to the functional storage element. Comparing outputs identifies delay-induced failures.
• Performance evaluation result cell (PERC) and PESE: Details the storage and reporting elements for performance evaluation and ageing-level recording.
• Operation states and control: Covers controller state diagrams, scan operations, and how PECLKs are applied at multiple delay points.
• Validation: Includes simulation and experimental results demonstrating behaviour and power trade-offs (power comparisons with prior work are provided).

Practical applications - who uses IEC TR 63133:2017

• Semiconductor design teams integrating on‑chip reliability monitoring into ASICs, SoCs, and IP.
• DFT and test engineers implementing scan chains and TAP-compatible ageing tests (note: IEEE 1149.1 TAP is referenced as a related test access mechanism).
• Reliability engineers and system integrators in aerospace, automotive, medical, and other safety‑critical industries who need proactive ageing diagnostics.
• Operations and maintenance teams using ageing-level outputs for decisions like device replacement, dynamic voltage‑frequency scaling (DVFS), or performance mode switching.

Benefits and implementation notes

• Enables in-field, fine-grained ageing detection without invasive external measurement.
• Supports dynamic selection of monitoring points using phase-shifted clocks and scan infrastructure.
• Helps extend safe operating life by converting measured ageing level into actionable reliability policies.

Related standards

• IEEE 1149.1 (boundary-scan / TAP) is referenced for test access port concepts and can be used alongside IEC TR 63133 implementations.

This technical report is valuable for teams adding embedded ageing monitoring to improve device lifetime awareness and system reliability.