IEC 61691-4:2004 PDF
Behavioural languages - Part 4: Verilog® hardware description language
Behavioural languages - Part 4: Verilog® hardware description language
- Статус документа:
- Отменён
- Формат:
- Электронный (PDF)
- Количество страниц:
- 855
- Дата публикации:
- 5 октября 2004 г.
- Издание:
- IEC IS 61691 edition 1 version 1
- ICS:
- 25.040.01
Contains the formal syntax and semantics of all Verilog HDL constructs; the formal syntax and semantics of Standard Delay Format (SDF) constructs; simulation system tasks and functions,such as text output display commands; compiler directives,such as text substitution macros and simulation time scaling; the Programming Language Interface (PLI) binding mechanism; the formal syntax and semantics of access routines,task/function routines,and Verilog procedural interface routines; informative usage examples; informative delay model for SDF; listings of header files for PLI This publication has the status of a double logo IEEE/IEC standard
Технические детали
- Технический комитет
- TC 91 - Electronics assembly technology
- SKU
- IEC 61691-4:2004
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