IEC 61691-6:2009 PDF

Name: IEC 61691-6:2009 — Behavioural languages - Part 6: VHDL Analog and Mixed-Signal Extensions
SKU: IEC 61691-6:2009
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Behavioural languages - Part 6: VHDL Analog and Mixed-Signal Extensions

Название (английский):

IEC 61691-6:2009

Behavioural languages - Part 6: VHDL Analog and Mixed-Signal Extensions

Статус документа:: Действующий
Формат:: Электронный (PDF)
Количество страниц:: 332
Дата публикации:: 14 декабря 2009 г.
Издание:: IEEE IS 61691 edition 1 version 1
ICS:: 25.040.01

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Описание (английский):

IEC 61691-6:2009(E) Defines IEC 61691-6/IEEE Std 1076.1 language, a hardware description language for the description and the simulation of analog, digital, and mixed-signal systems. The language, also informally known as VHDLAMS, is built on the IEC 61691-1-1/IEEE 1076 (VHDL) language and extends it to provide capabilities of writing and simulating analog and mixed-signal models.

Abstract

Похожие стандарты

Упомянутые в описании и другие стандарты IEC

Overview

IEC 61691-6:2009 (IEEE Std 1076.1) defines the VHDL Analog and Mixed‑Signal Extensions (commonly called VHDL‑AMS) - a hardware description language standard for describing and simulating analog, digital, and mixed‑signal systems. Built on the base VHDL language (IEC 61691‑1‑1 / IEEE 1076), this standard extends VHDL with language constructs and simulation semantics necessary for behavioral analog modeling, analog/digital interaction, and mixed‑signal system verification.

Key topics and technical requirements

The standard specifies language syntax, semantics and simulation requirements across these major areas:

Design hierarchy: entity/architecture declarations, configuration and component instantiation rules.

Subprograms & packages: procedures, functions, overloading, package bodies and conformance rules for reusable models.

Types & natures: scalar, composite, access, protected types and analog “natures” for continuous quantities.

Declarations & specifications: object, attribute, component and configuration specifications; disconnection and step‑limit specifications.

Expressions & statements: sequential and concurrent statements (signal/variable assignment, process, block, wait, assertions), operators and static/linear expressions.

Elaboration & execution: model elaboration rules, execution semantics, time handling, and interaction with the analog solver.

Analog solver support: language constructs and simulation directives to enable analog equation solving, frequency and noise calculation.

Lexical and environment: character set, literals, predefined packages (STANDARD, TEXTIO) and reserved words.

The document provides normative rules for language conformance and simulation behavior so models produce predictable results across compliant tools.

Applications

IEC 61691‑6:2009 is used where accurate behavioral description and simulation of mixed‑signal systems are needed:

Behavioral and system‑level modeling of mixed‑signal ICs (ADC/DAC, PLLs, power management).

Verification and pre‑silicon validation combining analog and digital blocks.

Creating analog/mixed‑signal testbenches and stimulus sources.

EDA tool development (simulators, analog solvers, language front‑ends).

Academic research and teaching in mixed‑signal design and simulation.

Related standards

IEC 61691‑1‑1 / IEEE Std 1076 - VHDL (base language)

IEEE Std 1076.1‑2007 - original IEEE VHDL‑AMS publication (equivalent reference)

Other IEC/IEEE behavioral language standards in the IEC 61691 series

Keywords: IEC 61691‑6, VHDL‑AMS, IEEE 1076.1, mixed‑signal modeling, analog solver, hardware description language, analog‑digital simulation.

IEC 61691-6:2009 PDF

Abstract

Похожие стандарты

Overview

Key topics and technical requirements

Applications

Who should use this standard

Related standards

Технические детали

BS IEC 61691-1-1:2011

Behavioural languages - VHDL Language reference manual

BS IEC 61691-6:2021

Behavioural languages - VHDL Analog and Mixed-Signal Extensions

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