IEC 62142:2005 PDF
Verilog (R) register transfer level synthesis
Название (английский):
IEC 62142:2005
Verilog (R) register transfer level synthesis
- Статус документа:
- Отменён
- Формат:
- Электронный (PDF)
- Количество страниц:
- 109
- Дата публикации:
- 27 июня 2005 г.
- Издание:
- IEC IS 62142 edition 1 version 1
- ICS:
- 25.040.99
Описание (английский):
Defines a set of modeling rules for writing Verilog® HDL descriptions for synthesis. Adherence to these rules guarantees the interoperability of Verilog HDL descriptions between register-transfer level synthesis tools that comply to this standard. The standard de.nes how the semantics of Verilog HDL are used, for example, to describe level- and edge-sensitive logic. It also describes the syntax of the language with reference to what shall be supported and what shall not be supported for interoperability.
Технические детали
- Технический комитет
- TC 91 - Electronics assembly technology
- SKU
- IEC 62142:2005