IEC 63011-3:2018 PDF

Name: IEC 63011-3:2018 — Integrated circuits - Three dimensional integrated circuits - Part 3: Model and measurement conditions of through-silicon via
SKU: IEC 63011-3:2018
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Integrated circuits - Three dimensional integrated circuits - Part 3: Model and measurement conditions of through-silicon via

Название (английский):

IEC 63011-3:2018

Integrated circuits - Three dimensional integrated circuits - Part 3: Model and measurement conditions of through-silicon via

Статус документа:: Действующий
Формат:: Электронный (PDF)
Количество страниц:: 28
Дата публикации:: 28 ноября 2018 г.
Издание:: IEC IS 63011 edition 1 version 1
ICS:: 01

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Описание (английский):

IEC 63011-3:2018 specifies a reference model of through-silicon via (TSV) electrical characteristics required for an interface design in three dimensional integrated circuit (3-D IC) to transmit and receive digital data and measurement conditions for resistance and capacitance to specify TSV characteristics in 3-D IC. Power devices, RF devices and micro-electromechanical systems (MEMS) are not in the scope of this document.

Abstract

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Overview

IEC 63011-3:2018 is an international standard developed by the International Electrotechnical Commission (IEC) that specifies a reference model and measurement conditions for the through-silicon via (TSV) - a critical technology in three-dimensional integrated circuits (3-D ICs). This part of the IEC 63011 series focuses on defining the electrical characteristics required for TSVs to ensure reliable transmission and reception of digital data in multi-chip 3-D IC implementations. The document details standardized methods for measuring TSV resistance and capacitance, vital for consistency and interoperability in digital consumer and mobile applications. Power devices, RF devices, and micro-electromechanical systems (MEMS) are explicitly excluded from its scope.

Key Topics

Through-Silicon Via Reference Model: The standard introduces a reference circuit model for the electrical characterization of TSVs, including considerations for capacitance and resistance. The model supports the interface design needed for digital data transmission in 3-D integrated circuits.

Measurement Conditions: IEC 63011-3:2018 establishes the measurement procedures and conditions for:

TSV resistance (using four-point measurement to isolate the resistance of the TSV from the surrounding structures).
TSV capacitance (impedance measurement to distinguish TSV capacitance from parasitic capacitances).
Frequency and voltage dependence of the TSV's electrical characteristics.

Scope and Exclusions: The standard is specifically tailored to digital consumer and mobile electronics, covering operating voltages from 0.1 V to 5 V and frequencies below 2 GHz. It excludes power devices, RF devices, and MEMS from its requirements.

Model Standardization Policy:

Resistance is defined as an average value.
Capacitance is waveform-defined, and fringe capacitance is removable.
Inductance is not considered due to minimal influence.
The model assumes the semiconductor substrate is connected to ground.

Applications

IEC 63011-3:2018 is highly relevant to manufacturers, designers, and test engineers working with advanced digital devices that leverage 3-D IC stacking. Key applications include:

Multi-Chip Module (MCM) Design: Enables accurate modeling and interface development for high-density multi-chip solutions, particularly in mobile phones, digital cameras, and tablets.

System on Chip (SoC) Integration: Facilitates the integration of heterogeneous technologies, allowing digital logic and memory to interface efficiently and reliably through standardized TSV designs.

Quality Assurance & Testing: Standardizes the performance measurement criteria, supporting consistent TSV characterization across the semiconductor industry. Ensures reliable high-speed, low-power interconnection essential in modern consumer electronics.

Design for Manufacturability: Provides guidelines that help in mitigating the effects of mechanical stress and maintain transistor reliability near TSV structures (keep-out zones).

Related Standards

IEC 63011-1: Integrated circuits – Three dimensional integrated circuits – Part 1: Terminology Offers definitions and terminology referenced throughout the IEC 63011 series.

IEC 63011 Series: This series encompasses multiple standards focused on 3-D ICs, covering terminology, models, and test methods for multi-chip integration.

Other IEC Semiconductor Standards: The 47A subcommittee and related IEC/ISO documents address further technical and test requirements relevant to semiconductor devices and interconnection technologies.

By adhering to IEC 63011-3:2018, industry professionals can ensure interoperability and high performance in the fast-evolving landscape of 3-D integrated circuit technology, supporting innovation and product reliability in the global electronics market. For more details or to purchase the official document, visit the IEC Webstore.

IEC 63011-3:2018 PDF

Abstract

Похожие стандарты

Overview

Key Topics

Applications

Related Standards

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