Overview
IEC TR 62856:2013, titled Documentation on Design Automation Subjects - The Bird's-eye View of Design Languages (BVDL), is a comprehensive technical report published by the International Electrotechnical Commission (IEC). This report provides an in-depth analysis and overview of thirty-three widely used electronic design languages essential for the System on a Chip (SoC) design ecosystem. Covering the full spectrum from system-level design to manufacturing data preparation, the standard is a critical resource for professionals involved in electronic design automation (EDA), semiconductor industries, and SoC development.
The standard’s primary goal is to present a clear, consolidated understanding of existing design languages, their features, and potential enhancements to support future development. It helps facilitate consistent EDA standardization across diverse design processes, thereby improving productivity, interoperability, and quality in electronic system design.
Key Topics
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Scope of Design Languages
The report surveys 33 design languages, such as UML, SystemC, VHDL, Verilog HDL, System Verilog, SPICE, and IP-XACT. It covers languages relevant to various stages of SoC design including:
- System level design and specification
- SoC implementation, verification, and IP block creation
- Analog/mixed-signal block design
- Interface data preparation for manufacturing
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Comprehensive Design Process Mapping
The BVDL documentation breaks down the design ecosystem into a chart and tables classified into:
- Electronic system design
- SoC design and verification
- Mixed-signal verification and analog design
- Characterization and IP preparation
This structure enables users to quickly identify which design languages apply to specific phases and roles in the SoC workflow.
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Standardization and Evolution
The report aids design language developers and technical managers by helping to:
- Assess language feature overlaps and redundancies
- Understand consistency within the evolving design ecosystem
- Address future challenges and emerging technological advances
It supports ongoing international collaboration toward harmonized EDA standards.
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Use Cases
Practical use cases include ensuring design flow consistency, monitoring language evolution, and anticipating new standardization demands driven by innovative technology trends.
Applications
IEC TR 62856:2013 serves a broad range of stakeholders in the electronics and semiconductor industries, especially:
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EDA Tool Developers:
Gain insights into supported languages, enabling more integrated design toolchains that span multiple phases of SoC development.
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Chip Designers and System Architects:
Identify appropriate languages for design specification, verification, and implementation-improving design quality and turnaround times.
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Standardization Bodies and Industry Consortia:
Use BVDL as a strategic reference to streamline standardization efforts, reduce duplication, and coordinate language development internationally.
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Academic and Research Institutions:
Utilize the report as a teaching resource and to guide research on design automation and language features suitable for next-generation SoC challenges.
Related Standards
The IEC TR 62856 complements other international standards and frameworks in the realm of electronic design automation including:
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Hardware Description Languages (HDL):
Standards such as IEEE VHDL, IEEE Verilog HDL, and SystemVerilog provide formal syntax and semantics for hardware modeling.
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Electronic System Level (ESL) Languages:
SystemC and SystemC-AMS standards for system-level modeling and mixed-signal simulation.
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Standardized Design Data Formats:
Formats such as DEF, LEF, Liberty, and IP-XACT facilitate interoperability between various EDA tools across the physical design and manufacturing interface stages.
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Verification Languages and Methodologies:
Standards like PSL (Property Specification Language) and UVM for hardware verification enhance design validation approaches.
By unifying the view of these languages and formats, IEC TR 62856 enhances global coordination and efficiency in SoC design automation.
Keywords:
IEC TR 62856, BVDL, design automation, System on a Chip, SoC design, electronic design languages, EDA standards, hardware description languages, design ecosystem, standardization, semiconductor design, verification languages, analog block design, IP block creation, electronic system design