Overview
ISO/IEC 13961:2000 - Information technology - Scalable Coherent Interface (SCI) - specifies an interconnect architecture and protocols that deliver computer-bus-like services using high-speed point-to-point links instead of a shared bus. SCI targets high-performance multiprocessor systems by supporting distributed shared memory with optional cache coherence and message-passing for loosely coupled systems. The standard defines packet formats, transaction sets (including read/write and efficient multiprocessor lock transactions), physical modules/connectors and initial link speeds (1 Gbyte/s parallel, 1 Gb/s serial), plus formal protocol specifications provided as computer programs.
Key topics and requirements
- Topology and physical models: support for rings, backplane rings, rectangular grids, switches and vendor-dependent interconnects to scale systems.
- Packet and protocol definitions: detailed logical packet formats, encodings, CRC/error checking, idle-symbol handling and protocol encodings.
- Transaction model: request/response queues, send/echo packets, move and broadcast transactions, and global-time synchronization primitives.
- Cache coherence: distributed directory-based coherence protocols, cache-line locks, sharing-list management and recovery mechanisms to tolerate transmission failures.
- Bandwidth & queue management: bandwidth allocation algorithms, ringlet priority, queue allocation and reservation rules to ensure fair access and avoid starvation.
- Reliability, availability and serviceability (RAS): autoconfiguration, transmission error detection/isolation, fault recovery (hardware/software), alternate routing and online replacement.
- Interoperability components: interchangeable module specification, connector and power definitions to support modular packaging.
- Formal specification: parts of the protocol are provided as executable/formalized programs to reduce ambiguity and improve implementability.
- Forward progress guarantees: protocols are designed to prevent deadlock and starvation even under multiprocessor conflicts.
Applications
- Designing high-performance symmetric multiprocessors (SMPs) and NUMA systems that need high-throughput interconnects.
- Building system backplanes, switches and interconnect modules for HPC, storage arrays and telecommunications equipment.
- Firmware, hardware and OS developers implementing distributed shared memory, cache-coherence agents, transaction handling and RAS features.
- Vendors requiring a standardized modular connector/power and interoperable packet protocol for multi-vendor systems.
Who should use this standard
- System architects and hardware engineers designing multiprocessor interconnects
- Firmware and OS developers implementing coherence and transaction semantics
- Vendors of backplane modules, switch fabrics and interconnect controllers
- Test and verification engineers using the formal protocol specifications
Related standards
- IEEE Std 1596 - equivalent source (SCI originally standardized by IEEE and adopted as ISO/IEC 13961).
Keywords: Scalable Coherent Interface, SCI, cache coherence, distributed shared memory, interconnect, multiprocessor, packet protocol, ring, switch, transaction set, high-performance computing.