Overview
ISO/IEC 14576:1999 defines the logical layer for the Synchronous Split Transfer type system bus (STbus). The standard specifies the protocol and logical interface for a high-performance, highly reliable system bus that uses a synchronous high-speed clock and a split transfer approach to minimize bus holding time and improve bus utilization. It is intended for use as a system or I/O bus in tightly coupled (TCMP) and loosely coupled (LCMP) multiprocessor systems.
Key topics and technical requirements
- Interface signals: Defines basic and optional bus interface signals and their semantics to ensure interoperability between function units.
- Bus operations and transfer protocol: Detailed command formats, transfer sequences, pipeline behavior, and arbitration mechanisms for bus masters and slaves.
- Data transfer types: Procedures for memory read/write, control space access, message transfer, and control register access.
- Cache coherency control: Specifies copyback and write-through coherency methods, cache block attributes (block size limited to 32 bytes), cache invalidation, retry indication, steal and steal-inhibit operations, and state transitions (I, SU, EM).
- Lock and synchronization operations: Support for lock transfer and related sequences to coordinate multiprocessor access.
- Error handling and reliability: Parity conventions (odd parity), error-reporting in answer transactions, fault detection methods, redundancy approaches and mechanisms to prevent fault propagation and support diagnosis.
- Auxiliary material: Informative annexes with performance estimates and lock/copyback interaction examples.
Applications and practical value
ISO/IEC 14576 (STbus logical layer) is practical for:
- Designing system buses and I/O buses in multiprocessor systems where low-latency, high-throughput shared access is required.
- Implementing cache-coherent multiprocessor platforms (both tightly and loosely coupled) that require well-defined copyback coherency and retry semantics.
- Hardware architects and SoC designers who need a standardized bus protocol for interoperability between CPUs, memory controllers, I/O adapters and bus handlers.
- Firmware and system integrators implementing bus arbitration, lock semantics, and error recovery consistent with international practice.
- Test, validation and verification teams evaluating bus protocol compliance, performance, and fault-handling behavior.
Who should use this standard
- Hardware architects and engineers designing multiprocessor boards and bus fabrics
- System integrators and OEMs building scalable CPU/memory/I/O subsystems
- Firmware developers implementing low-level bus protocols and coherency support
- Test engineers and compliance labs validating bus implementations
Related standards
ISO/IEC 14576 was prepared within ISO/IEC JTC 1 (microprocessor systems). Users will often consult other JTC 1 documents and industry bus-interface standards when designing complete hardware/software stacks to ensure broader interoperability and system integration.