Overview
ISO/IEC 18372:2004 specifies the RapidIO™ interconnect architecture as an open, high-performance, low-pin-count, packet-switched system-level interconnect. Targeted at networking, telecom and high-performance embedded systems, the standard defines an intra-system interface for chip-to-chip and board-to-board communications at gigabyte-per-second performance levels. It supports multiple programming models-globally shared memory, message passing and software-managed I/O-while providing low latency, high bandwidth and support for high-performance I/O devices.
Key topics and technical requirements
- Partitioned specification: The standard is organized into three main partitions covering:
- Input/Output Logical Specification (I) - system models, I/O operations (reads, writes, atomic operations), packet formats and I/O registers (Capability Registers/CARs, Command and Status Registers/CSRs).
- Message Passing Logical Specification (II) - data message and doorbell operations, message-passing packet formats and registers (mailbox and doorbell CSRs).
- Common Transport Specification (III) - transport formats, system topology (switch-based and ring-based), routing and common transport registers.
- Packet formats and routing: Detailed request/response packet types, field definitions and addressing/alignment rules for reliable packet-switched transport.
- Registers and control: Definitions for CARs, CSRs, mailbox and doorbell registers that enable device identity, capabilities, configuration and control.
- Link management and reliability: Link initialization/training, packet retry mechanisms and error recovery state machines (input/output port training, retry recovery and error recovery).
- System concerns: Operation ordering, transaction delivery semantics and deadlock considerations for system designers.
Practical applications
- High-performance embedded platforms requiring deterministic, low-latency communication between processors, memory engines and I/O devices.
- Telecom and networking equipment (line cards, switches, routers) where board-to-board and backplane interconnects demand high bandwidth and low pin count.
- Embedded signal processing, DSP-based systems and modular compute blades that use RapidIO™ for scalable, high-throughput intra-chassis communications.
Who should use this standard
- SoC architects, hardware and firmware engineers designing RapidIO™ interfaces.
- System integrators and board designers implementing switch- or ring-based topologies.
- Vendors of high-performance I/O devices, FPGA/ASIC designers and developers of embedded networking/telecom platforms.
Related standards
ISO/IEC 18372 complements other system interconnect standards and is typically considered alongside PCI Express, InfiniBand and Ethernet when evaluating intra-system vs. system-level interconnect strategies.
Keywords: ISO/IEC 18372:2004, RapidIO™, interconnect specification, packet-switched, intra-system interface, chip-to-chip, board-to-board, message passing, shared memory, CARs, CSRs, mailbox, doorbell, link initialization, error recovery.