IEC 60191-6-10:2003

Overview

IEC 60191-6-10:2003 - "Mechanical standardization of semiconductor devices - Part 6-10" defines the general rules, common outline drawings and dimensional requirements for P‑VSON (plastic very thin-profile small outline non‑lead) surface‑mounted semiconductor device packages. Published by the IEC in 2003, this first edition standardizes package outline geometry, terminal areas and key tolerances to ensure mechanical compatibility across manufacturers and PCB assembly processes.

Key topics

• Scope and definition: P‑VSON is a thin, flat, non‑lead plastic package whose terminals are on opposite sides of the package bottom and do not extend beyond the body.
• Outline drawings and nominal dimensions: Standardized body dimensions (D, E) and terminal pitch (e) series are specified to cover common P‑VSON sizes (body lengths from ~7 mm to 26 mm and widths from ~5 mm to 13 mm, with common pitch options such as 1.25, 1.00, 0.80, 0.65, 0.50 and 0.40 mm).
• Groups of dimensions:
  • Group 1 - dimensions and numerals that guarantee mechanical compatibility for mounting (e.g., seating/stand‑off heights, body height, terminal width plated, terminal thickness plated, overall width H and solder length L).
  • Group 2 - dimensions for fabrication and terminal position areas (e.g., unplated terminal widths, terminal position areas, terminal length L nominals and package overhang Z).
• Terminal geometry and counts: Tables provide recommended terminal widths, thickness ranges, and standard numbers of terminals (n) for combinations of body size and pitch.
• Tolerances and geometric controls: Key tolerances such as terminal position tolerance (x), coplanarity (y), flatness and seating plane definitions are included; ISO/DIS 2692 (geometrical tolerancing - MMR/LMR) is cited as normative for positional control.

Applications

This standard is essential for:

• Package designers creating P‑VSON product mechanical drawings.
• IC manufacturers and tooling engineers specifying terminal geometries.
• PCB designers and assembly engineers ensuring footprint compatibility and solder joint reliability.
• Contract manufacturers and test labs validating coplanarity, flatness and terminal placement.
• Quality and compliance teams checking components against recognized mechanical outlines.

Related standards

• IEC 60191 (all parts) - Mechanical standardization of semiconductor devices
• ISO/DIS 2692 - Geometrical product specification: MMR and LMR (referenced for positional tolerancing)

Keywords: IEC 60191-6-10, P-VSON, surface mounted semiconductor device packages, outline drawings, package dimensions, terminal pitch, coplanarity, mechanical standardization.