IEC 61691-1-1:2011

Overview - IEC 61691-1-1:2011 (VHDL Language Reference Manual)

IEC 61691-1-1:2011 (also published as IEEE Std 1076-2008) is the international Language Reference Manual (LRM) for VHDL - the standard behavioural language used for modelling, documenting and verifying electronic systems. This edition revises and enhances the VHDL LRM and importantly includes a standardized C language interface specification, bringing improved interoperability between VHDL simulators and C-based test or verification components. The publication is a double-logo IEEE/IEC standard and consolidates previously separate but related specifications to simplify maintenance.

Key topics and technical coverage

The standard provides formal definitions, syntax and semantics for VHDL; major technical topics include:

• Design entities, architectures and configurations - how modules are declared and instantiated
• Subprograms, packages and overloading - functions, procedures and reusable libraries
• Types and declarations - scalar, composite, access, protected and file types
• Sequential and concurrent statements - language constructs for processes, signal/variable assignment, control flow
• Expressions, operators and lexical elements - literal forms, identifiers and operators
• Scope, visibility and name resolution - use clauses, contexts and overload resolution
• Elaboration and execution model - how designs are elaborated and simulated at runtime
• Standard C language interface - specified interoperability with C for co-simulation and verification
• Verification-related features - constructs and extensions that support modern design verification methodologies

Practical applications

IEC 61691-1-1 is directly applicable to:

• RTL modelling and documentation for FPGA and ASIC designs
• Creating deterministic simulation models and testbenches for functional verification
• Integration of C-language test harnesses via the C interface (co-simulation, DPI-like use cases)
• Tool development for EDA vendors (simulators, synthesis, static analysis) that must conform to the VHDL LRM
• Academic and industrial training on VHDL syntax, semantics and best practices

Who should use this standard

• Hardware designers and verification engineers using VHDL
• EDA tool developers implementing VHDL language support and C interoperability
• System architects documenting electronic system behavior and interfaces
• Standards bodies and test labs validating tool conformance

Related standards

• IEEE Std 1076 (VHDL) - same content in IEEE format (double-logo)
• Complementary verification and assertion standards (commonly used alongside VHDL in industry workflows)

Keywords: VHDL, IEC 61691-1-1, VHDL Language Reference Manual, IEEE Std 1076, behavioural languages, C language interface, simulation, verification, electronic systems design, EDA tools.