IEC 62047-45:2025

Overview

IEC 62047-45:2025 defines an in‑situ, on‑chip measurement method for the impact resistance of nanostructures fabricated by silicon‑based micromachining for MEMS (micro‑electromechanical systems). The standard specifies design, fabrication and test‑method requirements for an on‑chip tester that applies controlled impact energy to nanostructures (for example cantilevers or fixed beams) and extracts their actual impact strength without specialized external instruments such as scanning probe microscopy or nanoindenters.

Key topics and requirements

• Scope: Measurement method for nanostructures made by microelectronic and other micromachining processes; intended for use in real manufacturing environments.
• In‑situ on‑chip tester: Integrates a testing structure and a testing device on a single chip (test structure, shock hammer, energy‑storage beam, fuse, baffle, anchor, load beam). The tester is axisymmetric and aligned so the impact hammer strikes the test structure along its symmetry axis.
• Design constraints: Energy‑storage beam dimensions (length l, width w), fuse width W, and displacement D must be chosen so the fuse will break at the designed stored energy while other tester parts remain intact. Designs must respect etch limits for line/gap sizes; Annex A gives example thermal‑drive designs and recommended dimensions.
• Fabrication: Tester must be fabricated with the same processes and materials as the target MEMS device (e.g., crystalline silicon movable layers). This allows implantation of the tester as a standard detection pattern on production wafers.
• Test method: A drive (off‑chip probe, on‑chip thermal drive, or on‑chip electrostatic drive) slowly increases force, moving the baffle until the fuse is broken and the impact hammer is released. Damage and deformation are then observed (electron or confocal microscope). Tests are repeated with different D values to find the minimum displacement that causes fracture; impact energy is computed per the method (see clause 5.4).
• Environment: Testing occurs in the actual manufacturing environment (on‑chip, on‑wafer) to capture process‑related variability (surface defects, linewidth loss, residual stress).

Applications and users

• Who benefits: MEMS process engineers, device designers, quality assurance teams, and reliability engineers.
• Practical uses: Inline process control, wafer‑level reliability assessment, design‑for‑manufacturing feedback, and bridging fabrication variability to design margins. Implanting the on‑chip tester as a standard detection pattern enables quantitative manufacturing feedback without specialized lab equipment.
• SEO keywords: IEC 62047-45:2025, MEMS impact resistance, in‑situ on‑chip tester, nanostructure testing, silicon MEMS fabrication, micromachining impact test.

Related standards

• Other parts of the IEC 62047 series addressing semiconductor MEMS topics and general ISO/IEC directives for standards development (see IEC website for the series list).