IEC 62047-47:2024

Overview

IEC 62047-47:2024 specifies an in‑situ measurement method for bending strength of microstructures fabricated by micromachining technology in silicon‑based MEMS. The standard defines requirements for an on‑chip tester (testing device + testing structure) that is fabricated with the same process and on the same wafer as the MEMS device, enabling on‑wafer, optical‑microscopy‑readable measurement of bending strength without requiring intricate instruments (for example scanning probe microscopy or nanoindenters).

Key topics and requirements

• Scope: Measurement of bending strength for microstructures manufactured by microelectronic and micromachining processes (silicon‑based MEMS).
• In‑situ on‑chip tester design:
  • Use a beam of constant strength to reduce stress‑concentration and extraction errors.
  • Include a testing device (displacement/deflection rulers, magnifying lever, elastic beam, on‑chip needlepoint, loading segment) to transfer and read force/displacement optically.
  • Drive options: off‑chip probe loading (example), on‑chip thermal or electrostatic actuation.
  • Ensure the elastic beam and bonding surfaces are stronger than the beam under test to force fracture in the test structure.
  • Loading segment length requirement: l > 20 μm to limit linewidth loss influence to <5%.
  • Ruler resolution must be compatible with optical microscopy.
  • Account for machining tolerances and surface roughness from process steps.
• Fabrication:
  • Tester and test structure must be fabricated using the same process as the MEMS device; applicable materials include movable structure layers such as crystalline silicon.
• Testing method:
  • Fix the chip on a probe station, apply horizontal load until fracture while observing under optical microscope, record deflection ruler reading d, and compute bending strength per the document’s formula.
• Environment: Testing should be carried out in the device’s actual manufacturing environment (on‑wafer/wafer‑level).

Applications and who uses it

• Process and reliability engineers: wafer‑level mechanical property monitoring and process control.
• MEMS designers: design validation and guidance for durable microstructure layouts and bonding areas.
• Semiconductor fabs & test labs: on‑chip qualification and batch‑level screening for defects/contamination that degrade bending strength.
• R&D teams: comparative material and process evaluation without specialized nanoindentation equipment.

Benefits include practical, low‑cost wafer‑level testing, reduced reliance on specialized metrology, and direct relevance because the tester is co‑fabricated with devices.

Related standards

• Part of the IEC 62047 series (Semiconductor devices – Micro‑electromechanical devices).
• Definitions reference IEC 62047‑45:2024 where applicable.