IEC 62050:2005
VHDL Register Transfer Level (RTL) synthesis
VHDL Register Transfer Level (RTL) synthesis
- Статус документа:
- Отменён
- Формат:
- Электронный (PDF)
- Количество страниц:
- 121
- Дата публикации:
- 19 июля 2005 г.
- Издание:
- IEC IS 62050 edition 1 version 1
- ICS:
- 25.040.01
Specifies a standard for use of very high-speed integrated circuit hardware description language (VHDL) to model synthesizable register-transfer level digital logic. A standard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset of the VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructs are identified that should be ignored or flagged as errors.
Технические детали
- Технический комитет
- TC 91 - Electronics assembly technology
- SKU
- IEC 62050:2005
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