IEC 63011-2:2018

Name: IEC 63011-2:2018 — Integrated circuits - Three dimensional integrated circuits - Part 2: Alignment of stacked dies having fine pitch interconnect
SKU: IEC 63011-2:2018
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Integrated circuits - Three dimensional integrated circuits - Part 2: Alignment of stacked dies having fine pitch interconnect

Название (английский):

IEC 63011-2:2018

Integrated circuits - Three dimensional integrated circuits - Part 2: Alignment of stacked dies having fine pitch interconnect

Статус документа:: Действующий
Формат:: Электронный (PDF)
Количество страниц:: 28
Дата публикации:: 28 ноября 2018 г.
Издание:: IEC IS 63011 edition 1 version 1
ICS:: 17.220.20

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Описание (английский):

IEC 63011-2:2018 provides specifications of initial alignment and alignment maintenance between multiple stacked integrated circuits during the die bonding process. These specifications define the alignment keys and operating procedures of the keys. These specifications apply only if electrical coupling method of die-to-die alignment is used in the die stacking.

Abstract

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Overview

IEC 63011-2:2018 is an international standard published by the International Electrotechnical Commission (IEC) that addresses the alignment of stacked dies in three-dimensional (3D) integrated circuits using fine pitch interconnect technology. Specifically, this standard provides detailed specifications for the initial alignment and ongoing alignment maintenance of multiple stacked integrated circuits during the die bonding process. It focuses on scenarios where die-to-die alignment is achieved through electrical coupling methods rather than traditional optical or mechanical systems. Ensuring precise alignment is critical for the proper electrical functionality and mechanical integrity of 3D integrated circuits, which are increasingly important in advanced electronics and semiconductor applications.

Key Topics

Initial Die Stacking Alignment
The standard outlines procedures for optical-based initial alignment of dies during stacking. It uses alignment keys-specialized patterns integrated on the dies-which serve as references for positioning. The image of the lower die’s alignment keys is stored and compared with those of the upper die during the alignment process, ensuring fine positional accuracy.

Alignment Maintenance During Bonding
After placing the upper die on the lower one, the bonding process involves thermal and mechanical stresses, posing a risk of misalignment. IEC 63011-2 specifies how to maintain alignment during this stage through real-time monitoring using electrical coupling methods, such as capacitive or inductive signals derived from the interconnects. These electrical signals act as feedback to detect and correct misalignments dynamically in the bonder apparatus.

Alignment Measurement After Stacking
Once stacking and bonding complete, the standard provides methods for assessing final alignment. This assessment helps verify that vertical interconnects and fine pitch wiring meet the accuracy and functional requirements necessary for reliable device performance.

Alignment Keys and Operating Procedures
Defined within this standard are various designs and dimensions for alignment keys optimized for electrical coupling sensing. These include mesh-type and conjugate detectors sensitive to misalignments in both X and Y directions. The operating procedures for using these keys ensure compatibility with die bonding machines and measurement tools.

Applications

Three-Dimensional Integrated Circuits (3D ICs)
IEC 63011-2 is essential for manufacturers developing 3D ICs where multiple semiconductor dies are vertically stacked with through-silicon vias (TSVs). These technologies enable improvements in performance, density, and functionality of chips without shrinking feature sizes. Precise alignment is crucial for ensuring effective electrical coupling and minimizing defects.

Semiconductor Die Bonding Equipment
Bonders equipped with electrical coupling capabilities utilize this standard to refine alignment accuracy, allowing for improved yield and reduced failure rates during assembly. This is particularly valuable in high-volume production environments focusing on next-generation semiconductor packaging.

Advanced Package Integration
The standard supports fine pitch interconnect technology used in heterogeneous integration where different types of semiconductor devices are stacked, such as logic, memory, and sensors, requiring intricate alignment and interconnect precision.

Related Standards

IEC 63011-1: Integrated Circuits – Three Dimensional Integrated Circuits – Part 1: Terminology
This complementary standard defines terms and basic concepts used in 3D ICs and serves as a foundational reference for understanding IEC 63011-2.

Standards on Die Bonding and Semiconductor Packaging
Other relevant international standards govern die attach processes, package assembly, and testing which work alongside IEC 63011-2 to ensure comprehensive quality management in 3D IC manufacturing.

Electrical Signal Coupling Technical Specifications
Standards describing capacitive and inductive coupling technologies are pertinent for implementing the electrical alignment methods recommended in IEC 63011-2.

By adhering to IEC 63011-2:2018, semiconductor manufacturers and equipment developers ensure high-precision alignment of stacked dies with fine pitch interconnects, enhancing the reliability and performance of three-dimensional integrated circuits. This standard is a vital resource for engineers, production managers, and quality control specialists focusing on state-of-the-art semiconductor packaging technologies.

IEC 63011-2:2018

Abstract

Похожие стандарты

Overview

Key Topics

Applications

Related Standards

Технические детали

IEC 63011-1:2018

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