ISO 6951:1986

Overview

ISO 6951:1986 - Information processing: Processor system bus interface (Eurobus A) defines the electrical, signalling and protocol rules for the Eurobus A processor-system bus. It is one member of a family of modular backplane interfaces designed for data acquisition, processing, communication and control systems in military, industrial and other applications. The standard specifies how devices (masters, slaves, arbiters, bus linkers) share a single backplane, including addressing, bus allocation, Read/Write/Vector cycles, and electrical and timing requirements.

Key topics and technical requirements

• Bus architecture and roles
  • Master/Slave model with an arbiter that allocates timedivision access to the bus.
  • Support for bus linkers to perform interbus transfers between separate Eurobus backplanes.
• Transfer types
  • Read cycle, Write cycle, and Vector cycle (address only).
  • Support for indivisible sequences (e.g., Read-Modify-Write) and retain/hold cycles.
• Data widths and addressing
  • Implementations may use 8, 16, 24, 32… bit data widths; logical implementations for 8–32 bits are in annexes A–D.
  • Address width designation (e.g., Eurobus 18/A) corresponds to highway bit count; data bits plus two equals the highway width.
  • Concepts of normal and pseudo address spaces for addressing flexibility.
• Electrical & timing
  • Detailed voltage levels, termination networks, transmitter/receiver characteristics and timing constraints are specified (clause 6 and annexes L, M, N).
  • Backplane maximum length 460 mm; asynchronous unbalanced voltage signalling supports transfer rates up to 6.5 × 10^6 words/bytes per second.
• Mechanical and interoperability
  • Connector allocations (annex E) and illustrative mechanical options (annex J) - e.g., Eurocard implementations and extender panels.
• Reliability and robustness
  • Procedures for timeout/abort of failed cycles, interrupt flagging to arbiter, and breaking interbus deadlocks (“deadly embrace”).

Applications and who uses it

ISO 6951:1986 is intended for:

• Hardware designers of backplanes, Eurocard-based systems and modular racks.
• System architects for embedded controllers, data acquisition, industrial control, and military electronics.
• Peripheral and interface manufacturers building DMA-capable devices, bus arbiters, bus linkers and spur cards.
• Integrators requiring a standard bus protocol for interoperability among mixed-width devices and multi-bus systems.

Practical uses include designing modular chassis with mixed-width peripherals, specifying connector pinouts, implementing arbiter logic and ensuring electrical/timing compliance for reliable high-throughput transfers.

Related standards

• ISO 6951 was prepared by ISO/TC 97 (Information processing systems). For broader system integration, consult other ISO bus-family documents and the ISO catalog for later revisions or related backplane standards.