IEC 63011-1:2018 PDF
Integrated circuits - Three dimensional integrated circuits - Part 1: Terminology
Integrated circuits - Three dimensional integrated circuits - Part 1: Terminology
- Статус документа:
- Действующий
- Формат:
- Электронный (PDF)
- Количество страниц:
- 24
- Дата публикации:
- 28 ноября 2018 г.
- Издание:
- IEC IS 63011 edition 1 version 1
- ICS:
- 31.200
IEC 63011-1:2018 provides definitions pertaining to multichip integrated circuits, as vertically stacked dies using through-silicon vias (TSVs) or micro bumps. Terms and definitions related to the fabrication and test of the multichip integrated circuits are also provided.
Abstract
Overview
is an international standard from the International Electrotechnical Commission (IEC) that establishes standardized terminology for three-dimensional integrated circuits (3D ICs). This document provides essential definitions related to multichip integrated circuits, specifically those employing vertically stacked dies interconnected with through-silicon vias (TSVs) or micro bumps. It serves as a foundational reference for stakeholders in semiconductor design, manufacturing, assembly, and testing of 3D integrated circuit technology.
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