ISO/IEC 10861:1994 PDF

Name: ISO/IEC 10861:1994 — Information technology — Microprocessor systems — High-performance synchronous 32-bit bus: MULTIBUS II
SKU: ISO/IEC 10861:1994
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Information technology — Microprocessor systems — High-performance synchronous 32-bit bus: MULTIBUS II

Название (английский):

ISO/IEC 10861:1994

Information technology — Microprocessor systems — High-performance synchronous 32-bit bus: MULTIBUS II

Статус документа:: Действующий
Формат:: Электронный (PDF)
Количество страниц:: 130
Дата публикации:: 15 декабря 1994 г.
Издание:: ISO/IEC IS 10861 edition 1 version 1
ICS:: 35.160

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Описание (английский):

Defines the operation, functions, and attributes of the IEEE 1296 bus standard. Defines a high-performance 32-bit synchronous bus standard. Intended for general purpose applications to optimize block transfers, including protocol for message passing. Intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system and heterogeneous processor types in the same system.

Abstract

Похожие стандарты

Другие стандарты ISO

Overview

ISO/IEC 10861:1994 (ANS/IEEE Std 1296) specifies MULTIBUS II, a high‑performance synchronous 32‑bit system bus for microprocessor systems. The standard defines the operation, functions and attributes of the IEEE 1296 parallel system bus (PSB), including signal definitions, protocol, electrical characteristics and mechanical requirements. MULTIBUS II targets a 32‑bit multiplexed address/data backplane with a 10 MHz bus clock and supports message‑passing, error detection and retry mechanisms to enable reliable, high‑bandwidth block transfers (typical aggregate throughput 32–40 Mbyte/s).

Key topics and technical requirements

Bus architecture: 32‑bit synchronous multiplexed address/data path designed for backplane systems and multiple‑processor configurations.

Timing: Synchronous operation at a 10 MHz bus clock (protocol and AC timing specified).

Address spaces: Defined memory, I/O, message and geographic addressing models to support dynamic system configuration.

Message‑passing protocol: High‑level protocol for message transfer with error detection, retry and negative acknowledge semantics to enhance reliability.

Error handling: Parity and message retry mechanisms to detect and recover from transfer errors.

Arbitration and transfer rules: Protocol for bus arbitration, transfer initiation, and completion to support concurrent transfers.

Electrical & mechanical specs: DC/AC characteristics, pin assignments and backplane mechanical requirements for interoperable module designs.

VLSI implementation guidance: Design intended to allow cost‑effective VLSI interface chips so modules can achieve near‑maximum bus utilization.

Applications and practical value

Building multiprocessor embedded systems and industrial controllers that require deterministic, high‑bandwidth interconnects.

Designing backplane‑based systems (card cages and chassis) where heterogeneous processor modules coexist.

Implementing message‑oriented interprocessor communication, enabling whole‑board subsystems to act as independent processing nodes.

Guiding hardware engineers and VLSI designers when developing bus interface controllers, PHYs and compliant modules.

Supporting maintenance, interoperability and standard compliance for legacy MULTIBUS II installations.

Who uses this standard

System architects and hardware designers specifying backplane interconnects.

Embedded systems integrators and OEMs assembling heterogeneous processor boards.

VLSI/ASIC developers implementing bus interface logic.

Test engineers and maintainers working with MULTIBUS II / IEEE 1296 systems or migrating legacy equipment.

Related standards

IEEE Std 1296 (MULTIBUS II) - identical technical basis adopted by ISO/IEC 10861.

MULTIBUS I / IEEE Std 796 - earlier MULTIBUS family reference discussed in the standard introduction.

Keywords: ISO/IEC 10861, MULTIBUS II, IEEE 1296, high‑performance synchronous 32‑bit bus, message passing, multiplexed address/data, geographic addressing, 10 MHz bus clock, backplane bus.

ISO/IEC 10861:1994 PDF

Abstract

Похожие стандарты

Overview

Key topics and technical requirements

Applications and practical value

Who uses this standard

Related standards

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