ISO/IEC 13213:1994 PDF

Overview

ISO/IEC 13213:1994 - "Information technology - Microprocessor systems - Control and Status Registers (CSR) Architecture for microcomputer buses" defines a standardized CSR model for nodes on microcomputer buses. The standard specifies address-space maps, bus transaction sets, node CSR layouts and the format/content of a configuration ROM used to autoconfigure systems built from non-processor nodes supplied by multiple vendors. Annexes provide background and rationale to aid implementation and interoperability.

Key topics and technical requirements

• CSR address spaces and unit architectures
  • Defines contiguous address spaces (initial, indirect, extended units) that map to vendor-defined unit register sets.
  • Units typically have private register sets; a few CSRs are shared across units.
• Interrupt architecture
  • INTERRUPT-TARGET: standardized CSR offset for broadcast and directed interrupts; supports immediate queuing of multiple interrupt writes and 32 interrupt-group bits.
  • STATE-CLEAR: standardized status/clear register that contains unit-specific Service-request bits to aid polled interrupt dispatch and clearing of status bits.
  • Polling model for shared interrupt-group bits and recommendations for interrupt dispatch tables (node pointer, mask, dispatch params).
  • Directed interrupts are constrained to write transactions and may be delayed by a busy status to avoid deadlocks.
• Message passing
  • Standard CSR offsets for request and response messages (separate targets to avoid queue deadlocks).
  • All message-capable nodes must support 64‑byte messages; larger messages may be implemented with concatenation or indirection (DMA).
  • Hardware must provide at least one queue entry per message-passing address; queued messages are processed by firmware/software.
• Globally synchronized clocks
  • Partially standardized clock-unit registers and formats: CLOCK VALUE (64‑bit unsigned fixed-point: 32s seconds / 32s fractional), CLOCK-TICK-PERIOD, CLOCK-STROBE-ARRIVED.
  • Synchronization models: clock sampling via strobe, reference update (master or averaged), and clock adjustment (master updates or local updates).
  • Read/write protocols for 64-bit clock registers (multi-32-bit access sequences) to ensure consistent time reads.

Practical applications and audience

• System architects and hardware designers implementing microcomputer bus nodes (processors, memory controllers, I/O devices, bridges).
• Firmware and OS developers responsible for I/O drivers, interrupt dispatch, message handling and time services.
• Vendors building interoperable non-processor nodes and integrators designing autoconfiguration schemes using the configuration ROM.
• Useful for systems requiring standardized broadcast interrupts, message queues, and distributed clock synchronization.

Related standards and notes

• The document is aligned with ANSI/IEEE Std 1212 (1994) references and mentions applicability to point-to-point link standards (e.g., SCI) for certain clock-strobe behaviors.
• Keywords: ISO/IEC 13213:1994, CSR Architecture, Control and Status Registers, microcomputer buses, interrupts, message passing, clock synchronization, configuration ROM, autoconfigure.